1. Field of the Invention
The present invention relates to designing semiconductor devices, and particularly, to a method of designing wiring structures of LSIs and wiring structures designed accordingly.
2. Description of the Related Art
To increase the scale of LSIs, fine technology for LSI elements is improving. As LSI elements become smaller, process-originated variations occurring on LSI elements during, for example, patterning and ion-implanting processes become and not negligible in connection with the characteristics of LSIs. This is described in, for example, N. Shigyo et al., “Statistical of MOSFETs using TCAD: Meshing noise problem and selection of factors,” Proc. IWSM98, p. 10, 1998.
One study based on sensitivity analyses about the influence of process-originated variations on the characteristics of a circuit is disclosed in Z. J. Lin and C. J. Sponos, “Sensitivity study of interconnect variation using statistical experimental design,” Proc. IWSM, p. 68, 1998. Another study based on analytic formulas is disclosed in O. S. Nakagawa et al., “Modeling of pattern-dependent on-chip interconnect geometry variation for deep-submircon process and design technology,” Tech. Dig. IEDM, p. 137, 1997.
One of the important characteristics of an LSI is a delay time. The delay time of an LSI circuit is given by the product RC of the resistance R and capacitance C of wiring of the circuit if the wiring is long. If the wiring is short, the dealy time of the circuit is the product RtrC of the transistor ON resistance Rtr and capacitance C of the wiring. This is described in H. B. Bakoglu and J. D. Meindl, “Optimal interconnection circuits for VLSI,” IEEE Trans. Electron Devices, ED-32, p. 903, 1985. Namely, when considering characteristic of wiring, an important factor to determine the delay of an LSI circuit is the product RC of wiring of the circuit if the wiring is long, and it is the capacitance C of the wiring if the wiring is short.
When forming an LSI with fine elements, it is necessary to reduce the capacitance C and resistance-by-capacitance RC of wiring of the LSI. It is also necessary to suppress a capacitance variation ratio ΔC/C and resistance-by-capacitance variation ratio Δ(RC)/(RC) caused by process-originated variations. There is a need for a wiring structure having suppressed C and ΔC as well as suppressed RC and Δ(RC)/(RC).
The prior arts merely analyze the influence of process-originated variations on circuit characteristics, and there is no prior art that suggests or provides a guideline for a wiring structure capable of suppressing variation ratios ΔC/C and Δ(RC)/(RC) caused by process-originated variations.